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1

A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

Apperson, Ryan W., Yu, Zhiyi, Meeuwsen, Michael J., Mohsenin, Tinoosh, Baas, Bevan M.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 1.50 MB

english, 2007

2

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Stillmaker, Aaron, Baas, Bevan

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.17 MB

english, 2017

3

[IEEE 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009 - Taipei, Taiwan (2009.05.24-2009.05.27)] 2009 IEEE International Symposium on Circuits and Systems - The design of a reconfigurable continuous-flow mixed-radix FFT processor

Jacobson, Anthony T., Truong, Dean N., Baas, Bevan M.

Year:

2009

Language:

english

File:

PDF, 581 KB

english, 2009

4

[IEEE 2017 IEEE Conference on Dependable and Secure Computing - Taipei, Taiwan (2017.8.7-2017.8.10)] 2017 IEEE Conference on Dependable and Secure Computing - A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS

Braly, Michael, Stillmaker, Aaron, Baas, Bevan

Year:

2017

Language:

english

File:

PDF, 989 KB

english, 2017

5

A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

Tinoosh Mohsenin, Bevan M. Baas

Journal:

Journal of Signal Processing Systems

Year:

2010

Language:

english

File:

PDF, 860 KB

english, 2010

6

[IEEE 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009 - Taipei, Taiwan (2009.05.24-2009.05.27)] 2009 IEEE International Symposium on Circuits and Systems - Multi-Split-Row Threshold decoding implementations for LDPC codes

Mohsenin, Tinoosh, Truong, Dean, Baas, Bevan

Year:

2009

Language:

english

File:

PDF, 692 KB

english, 2009

7

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Dynamic voltage and frequency scaling circuits with two supply voltages

Cheng, Wayne H., Baas, Bevan M.

Year:

2008

Language:

english

File:

PDF, 274 KB

english, 2008

8

Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms

Foroozannejad, Mohammad H., Hashemi, Matin, Mahini, Alireza, Baas, Bevan M., Ghiasi, Soheil

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 12.72 MB

english, 2014

9

[IEEE 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009 - Taipei, Taiwan (2009.05.24-2009.05.27)] 2009 IEEE International Symposium on Circuits and Systems - A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

Tran, Anh T., Truong, Dean N., Baas, Bevan M.

Year:

2009

Language:

english

File:

PDF, 423 KB

english, 2009

10

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - A low-area interconnect architecture for chip multiprocessors

Zhiyi Yu,, Baas, Bevan M.

Year:

2008

Language:

english

File:

PDF, 151 KB

english, 2008

11

[IEEE 2011 IEEE International Symposium on Circuits and Systems (ISCAS) - Rio de Janeiro, Brazil (2011.05.15-2011.05.18)] 2011 IEEE International Symposium of Circuits and Systems (ISCAS) - Low power LDPC decoder with efficient stopping scheme for undecodable blocks

Mohsenin, Tinoosh, Shirani-mehr, Houshmand, Baas, Bevan

Year:

2011

Language:

english

File:

PDF, 271 KB

english, 2011

12

[IEEE 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) - Fort Collins, CO, USA (2015.8.2-2015.8.5)] 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) - Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling

Liu, Bin, Foroozannejad, Mohammad H., Ghiasi, Soheil, Baas, Bevan M.

Year:

2015

Language:

english

File:

PDF, 341 KB

english, 2015

13

Corrigendum to “Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm” [Integr. VLSI J. 58 (2017) 74–81]

Stillmaker, Aaron, Baas, Bevan

Journal:

Integration, the VLSI Journal

Year:

2019

Language:

english

File:

PDF, 168 KB

english, 2019

14

Architecture and Evaluation of an Asynchronous Array of Simple Processors

Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas

Journal:

Journal of Signal Processing Systems

Year:

2008

Language:

english

File:

PDF, 538 KB

english, 2008

15

Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

Tran, Anh T., Baas, Bevan M.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.89 MB

english, 2014

16

[IEEE 2012 IEEE 18th International Conference on Parallel and Distributed Systems (ICPADS) - Singapore, Singapore (2012.12.17-2012.12.19)] 2012 IEEE 18th International Conference on Parallel and Distributed Systems - Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array

Stillmaker, Aaron, Stillmaker, Lucas, Baas, Bevan

Year:

2012

Language:

english

File:

PDF, 508 KB

english, 2012

17

[IEEE 2011 45th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2011.11.6-2011.11.9)] 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) - A high-performance area-efficient AES cipher on a many-core platform

Liu, Bin, Baas, Bevan M.

Year:

2011

Language:

english

File:

PDF, 119 KB

english, 2011

18

Parallel AES Encryption Engines for Many-Core Processor Arrays

Liu, Bin, Baas, Bevan M.

Journal:

IEEE Transactions on Computers

Year:

2013

Language:

english

File:

PDF, 1.87 MB

english, 2013

19

[IEEE 2010 IEEE Biomedical Circuits and Systems Conference (BioCAS) - Paphos, Cyprus (2010.11.3-2010.11.5)] 2010 Biomedical Circuits and Systems Conference (BioCAS) - Massively parallel processor array for mid-/back-end ultrasound signal processing

Truong, Dean N., Baas, Bevan M.

Year:

2010

Language:

english

File:

PDF, 256 KB

english, 2010

20

A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders

Mohsenin, Tinoosh, Truong, Dean N, Baas, Bevan M

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2010

Language:

english

File:

PDF, 1.68 MB

english, 2010

21

[IEEE 2011 IEEE 29th International Conference on Computer Design (ICCD 2011) - Amherst, MA, USA (2011.10.9-2011.10.12)] 2011 IEEE 29th International Conference on Computer Design (ICCD) - RoShaQ: High-performance on-chip router with shared queues

Tran, Anh T., Baas, Bevan M.

Year:

2011

Language:

english

File:

PDF, 1.17 MB

english, 2011

22

[IEEE 2010 IEEE Workshop On Signal Processing Systems (SiPS) - San Francisco, CA, USA (2010.10.6-2010.10.8)] 2010 IEEE Workshop On Signal Processing Systems - DLABS: A dual-lane buffer-sharing router architecture for networks on chip

Tran, Anh T., Baas, Bevan M.

Year:

2010

Language:

english

File:

PDF, 263 KB

english, 2010

23

A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System

Xiao, Zhibin, Baas, Bevan M.

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

2011

Language:

english

File:

PDF, 1021 KB

english, 2011

24

[IEEE 2008 42nd Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2008.10.26-2008.10.29)] 2008 42nd Asilomar Conference on Signals, Systems and Computers - A complete real-time 802.11a baseband receiver implemented on an array of programmable processors

Tran, Anh T., Truong, Dean N., Baas, Bevan M.

Year:

2008

Language:

english

File:

PDF, 314 KB

english, 2008

25

[IEEE 2008 42nd Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2008.10.26-2008.10.29)] 2008 42nd Asilomar Conference on Signals, Systems and Computers - A thresholding algorithm for improved Split-Row decoding of LDPC codes

Mohsenin, Tinoosh, Urard, Pascal, Baas, Bevan

Year:

2008

Language:

english

File:

PDF, 262 KB

english, 2008

26

[IEEE 2008 IEEE International Conference on Computer Design (ICCD) - Lake Tahoe, CA, USA (2008.10.12-2008.10.15)] 2008 IEEE International Conference on Computer Design - A high-performance parallel CAVLC encoder on a fine-grained many-core system

Xiao, Zhibin, Baas, Bevan

Year:

2008

Language:

english

File:

PDF, 1.02 MB

english, 2008

27

[IEEE 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2009.11.1-2009.11.4)] 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers - Trends and challenges in LDPC hardware decoders

Mohsenin, Tinoosh, Baas, Bevan

Year:

2009

Language:

english

File:

PDF, 220 KB

english, 2009

28

[IEEE 2011 45th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2011.11.6-2011.11.9)] 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) - A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform

Xiao, Zhibin, Le, Stephen, Baas, Bevan

Year:

2011

Language:

english

File:

PDF, 235 KB

english, 2011

29

[IEEE 2011 45th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2011.11.6-2011.11.9)] 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) - A reduced routing network architecture for partial parallel LDPC decoders

Shirani-Mehr, Houshmand, Mohsenin, Tinoosh, Baas, Bevan

Year:

2011

Language:

english

File:

PDF, 401 KB

english, 2011

30

[IEEE 2006 International Conference on Computer Design - San Jose, CA, USA (2007.10.1-2007.10.4)] 2006 International Conference on Computer Design - Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles

Yu, Zhiyi, Baas, Bevan

Year:

2006

Language:

english

File:

PDF, 592 KB

english, 2006

31

[IEEE 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) - Santa Cruz, CA, USA (2012.10.7-2012.10.10)] 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) - A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture

Xiao, Zhibin, Baas, Bevan

Year:

2012

Language:

english

File:

PDF, 1.87 MB

english, 2012

32

[IEEE 2014 48th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2014.11.2-2014.11.5)] 2014 48th Asilomar Conference on Signals, Systems and Computers - Scalable hardware-based power management for many-core systems

Liu, Bin, Bohnenstiehl, Brent, Baas, Bevan M.

Year:

2014

Language:

english

File:

PDF, 271 KB

english, 2014

33

Guest Editors' Introduction to Practical Parallel EDA

Topaloglu, Rasit Onur, Baas, Bevan

Journal:

IEEE Design and Test

Year:

2013

Language:

english

File:

PDF, 64 KB

english, 2013

34

[IEEE 2015 49th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2015.11.8-2015.11.11)] 2015 49th Asilomar Conference on Signals, Systems and Computers - Area efficient backprojection computation with reduced floating-point word width for SAR image formation

Pimentel, Jon J., Stillmaker, Aaron, Bohnenstiehl, Brent, Baas, Bevan M.

Year:

2015

File:

PDF, 1.41 MB

2015

35

[IEEE 2015 49th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2015.11.8-2015.11.11)] 2015 49th Asilomar Conference on Signals, Systems and Computers - A software LDPC decoder implemented on a many-core array of programmable processors

Bohnenstiehl, Brent, Baas, Bevan

Year:

2015

Language:

english

File:

PDF, 245 KB

english, 2015

36

[IEEE 2015 49th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2015.11.8-2015.11.11)] 2015 49th Asilomar Conference on Signals, Systems and Computers - Area efficient backprojection computation with reduced floating-point word width for SAR image formation

Pimentel, Jon J., Stillmaker, Aaron, Bohnenstiehl, Brent, Baas, Bevan M.

Year:

2015

Language:

english

File:

PDF, 1.41 MB

english, 2015

37

[IEEE 2014 48th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2014.11.2-2014.11.5)] 2014 48th Asilomar Conference on Signals, Systems and Computers - Hybrid floating-point modules with low area overhead on a fine-grained processing core

Pimentel, Jon J., Baas, Bevan M.

Year:

2014

Language:

english

File:

PDF, 441 KB

english, 2014

38

[IEEE 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) - Santa Cruz, CA, USA (2012.10.7-2012.10.10)] 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) - A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture

Xiao, Zhibin, Baas, Bevan

Year:

2012

Language:

english

File:

PDF, 1.87 MB

english, 2012

39

A Shared Memory Module for Asynchronous Arrays of Processors

Meeuwsen, Michael J., Yu, Zhiyi, Baas, Bevan M.

Journal:

EURASIP Journal on Embedded Systems

Year:

2006

Language:

english

File:

PDF, 994 KB

english, 2006

40

[IEEE 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip - La Jolla, CA, USA (2009.05.10-2009.05.13)] 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip - A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network

Tran, Anh T., Truong, Dean N., Baas, Bevan M.

Year:

2009

Language:

english

File:

PDF, 363 KB

english, 2009

41

Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs

Pimentel, Jon J., Bohnenstiehl, Brent, Baas, Bevan M.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 4.76 MB

english, 2016

42

[ACM Press the 47th Design Automation Conference - Anaheim, California (2010.06.13-2010.06.18)] Proceedings of the 47th Design Automation Conference on - DAC '10 - Circuit modeling for practical many-core architecture design exploration

Truong, Dean N., Baas, Bevan M.

Year:

2010

Language:

english

File:

PDF, 235 KB

english, 2010

43

Editorial

Chakrabarty, Krishnendu, Alioto, Massimo, Baas, Bevan M., Boon, Chirn Chye, Chang, Meng-Fan, Chang, Naehyuck, Chang, Yao-Wen, Chang, Chip-Hong, Chang, Shih-Chieh, Chen, Poki, Chowdhury, Masud, Corsone

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2017

Language:

english

File:

PDF, 4.70 MB

english, 2017

44

KiloCore: A 32-nm 1000-Processor Computational Array

Bohnenstiehl, Brent, Stillmaker, Aaron, Pimentel, Jon J., Andreas, Timothy, Liu, Bin, Tran, Anh T., Adeagbo, Emmanuel, Baas, Bevan M.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2017

Language:

english

File:

PDF, 4.55 MB

english, 2017

45

[IEEE 2006 IEEE Hot Chips 18 Symposium (HCS) - Stanford, CA, USA (2006.8.20-2006.8.22)] 2006 IEEE Hot Chips 18 Symposium (HCS) - Hardware and applications of AsAP: An asynchronous array of simple processors

Baas, Bevan, Zhiyi Yu,, Meeuwsen, Michael, Sattari, Omar, Apperson, Ryan, Work, Eric, Webb, Jeremy, Lai, Michael, Gurman, Daniel, Chi Chen,, Cheung, Jason, Truong, Dean, Mohsenin, Tinoosh

Year:

2006

Language:

english

File:

PDF, 1.15 MB

english, 2006

46

[IEEE 2016 IEEE Hot Chips 28 Symposium (HCS) - Cupertino, CA, USA (2016.8.21-2016.8.23)] 2016 IEEE Hot Chips 28 Symposium (HCS) - KiloCore: A 32 nm 1000-processor array

Bohnenstiehl, Brent, Stillmaker, Aaron, Pimentel, Jon, Andreas, Timothy, Bin Liu,, Tran, Anh, Adeagbo, Emmanuel, Baas, Bevan

Year:

2016

Language:

english

File:

PDF, 7.61 MB

english, 2016

47

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Mohsenin, Tinoosh, Shirani-mehr, Houshmand, Baas, Bevan M.

Journal:

Year:

2013

Language:

english

File:

PDF, 1.94 MB

english, 2013

48

[IEEE 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) - Windsor, ON, Canada (2018.8.5-2018.8.8)] 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) - A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding

Wu, Shifu, Baas, Bevan

Year:

2018

File:

PDF, 993 KB

2018

49

Corrigendum to “Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm” [Integr. VLSI J. 58 (2017) 74–81]

Stillmaker, Aaron, Baas, Bevan

Journal:

Integration, the VLSI Journal

Year:

2019

File:

PDF, 168 KB

2019

50

Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop

Ogunfunmi, Tokunbo, McAllister, John, Baas, Bevan, Chakraborty, Mrityunjoy

Journal:

Journal of Signal Processing Systems

Year:

2020

File:

PDF, 109 KB

2020